1. Field of the Invention
The present invention relates to a semiconductor device fabrication method.
2. Description of the Related Art
In order to realize higher integration in large scale integrated (LSI) circuits, a three dimensional arrangement of device constituent elements has been expected. For example, cylindrical capacitors enabling relatively high capacitance through an increase in an electrode area while keeping a small footprint in a substrate is attracting much attention in the case of a memory device such as a dynamic random access memory (DRAM). Accordingly, a method for fabricating such an electrode for the capacitor has been proposed, for example, in Japanese Patent Application Publication No. 2008-135632.
In addition, as far as an active device is concerned, in order to solve a problem of an increased leakage current caused by reduction of a gate length in a planar field effect transistor (FET), much attention has been attracted by a fin field effect transistor (Fin-FET) enabling further miniaturization while keeping the leakage current at a low level (see Digh Hisamoto, Toru Kaga, Eiji Takeda, “Impact of the Vertical SOI “DELTA” Structure on Planar Device Technology” IEEE TRANSACTIONS ON ELECTRON DEVICES Vol. 38 No. 6, June 1991) and a stacked-surrounding gate transistor (S-SGT) enabling high speed performance and low consumption of electricity while keeping a smaller footprint (see T. Endoh, K. Shinmei, H. Sakuraba and F. Masuoka, “The analysis of the stacked-surrounding gate transistor (S-SGT) DRAM for the high speed and low voltage operation”, IEICE Trans. Electron., vol. E81-C, No. 9, p. 1491, 1998).
Such a three dimensional arrangement makes it possible to realize a LSI circuit with higher integration and high performance.
In order to realize the three-dimensional device mentioned above, further miniaturization of device constituent elements is indispensable, and thus an extreme ultraviolet photolithography technology utilizing extreme ultraviolet (EUV) light having a wavelength of 13.5 nm, for example, is under vigorous development in order to realize a dimension lower than a critical dimension that can be realized by conventional or current photolithography technology. However, such photolithography technology has not been in practical use partly because it takes a long time to expose a photoresist film when using EUV light. Therefore, another semiconductor device fabrication method that does not rely on such photolithography has long been desired in order to realize a miniaturized three-dimensional device without waiting for the advent of new photolithography technologies including the EUV photolithography.
The present invention has been made in view of the above, and is directed to a semiconductor device fabrication method that enables fabricating a miniaturized three-dimensional semiconductor device.